1. Field of the Invention
Embodiments of the present invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to parallel bit test (PBT) circuits and methods of testing memory cells in semiconductor memory devices using the PBT circuits.
A claim of priority is made to Korean Patent Application No. 10-2006-51618, filed on Jun. 8, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Semiconductor memory devices are typically manufactured by performing several design and processing steps on a semiconductor wafer. Following manufacture, the semiconductor memory devices are then tested for defects. This testing often occurs both after performing the processing steps on the semiconductor wafer and after the semiconductor memory devices are packaged. The testing performed after processing the wafer is commonly referred to as a wafer test, and the testing performed after packaging the devices is commonly referred to as a package test.
In general, semiconductor memory devices include a huge number of memory cells. When testing semiconductor memory devices, preferably each of the memory cells is tested for defects. In practice, it is very difficult to manufacture a semiconductor memory device without any defects at all. Accordingly, to address this problem, semiconductor devices often include redundant memory cells adapted to function in place of defective memory cells. However, in order for the redundant memory cells to function in place of the defective memory cells, the defective memory cells must typically be identified so that a compensation or repair function can be performed to establish the redundant memory cells to function in place of the defective cells.
One way to identify defective memory cells in a semiconductor memory device is through a parallel bit test. A parallel bit test (PBT) is generally performed by a PBT circuit in the semiconductor memory device under the control of a test apparatus. The test apparatus sends a command to the semiconductor memory to establish a test mode for the PBT. Two common test modes include a wafer test mode for performing a wafer test and a package test mode for performing a package test.
Once the test mode is established, the test apparatus sends write commands to the semiconductor memory device to write a test data pattern to memory cells in the semiconductor memory device. Once the test data pattern is written in the memory cells, the test apparatus sends read commands to the semiconductor device to cause the PBT circuit to test whether the test data pattern was properly written in the memory cells. The PBT circuit tests whether the test data pattern was properly written in the memory cells by examining pairs of memory cells that are supposed to store the same data based on the test data pattern. In other words, the PBT circuit compares data stored in pairs of memory cells and where the same data is stored in both memory cells of the pair, the memory cells are considered to be functioning correctly. On the other hand, where different data is stored in both memory cells of the pair, one or more memory cells in the pair are determined to be defective.
As an example, FIG. 1 is a conceptual diagram illustrating a conventional parallel bit test method for a semiconductor memory device. Referring to FIG. 1, the semiconductor memory device comprises first through fourth memory blocks 10, 11, 12, and 13. Each of memory blocks 10, 11, 12, and 13 comprises four input-output (IO) lines adapted to input or output four bits at a time. In a PBT test mode, 4 bits of parallel data output from each of memory blocks 10, 11, 12, and 13 are divided into pairs and the bits in each pair are compared with each other.
The parallel bit test method will be described in more particular detail with reference to memory block 10 in FIG. 1. The method performed in relation to memory block 10 is similar to the method performed in relation to memory blocks 11 through 13 and therefore, detailed descriptions of the operation of memory blocks 11 through 13 is omitted to avoid redundancy.
Memory block 10 stores bits D10 through D13. In the PBT test mode, bits D10 and D12 are compared with each other in a first primary comparison and bits D11 and D13 are compared with each other in a second primary comparison. After the first and second primary comparisons are performed, results of the first and second primary comparison are combined in a secondary comparison to produce an output signal on an IO pin DQ0. The first and second primary comparisons are typically performed by performing an XOR operation on two bits. The secondary comparison is then performed by performing an OR operation on results of the respective first and second primary comparisons. Accordingly, where the two bits in the first primary comparison are the same, the XOR operation of the first primary comparison will result in an output of a logical “0”. Similarly, where the two bits in the second primary comparison are the same, the XOR operation of the second primary comparison will result in an output of logical “0”. Where both the first and second primary comparisons result in an output of logical “0”, the OR operation of the secondary comparison will result in a logical “0”, indicating a successful parallel bit test. However, if any pair of bits are different in the first or second primary comparisons, the XOR operation of the first or second primary comparison will result in an output of logical “1” on IO pin DQ0, and therefore, the OR operation of the secondary comparison will result in an output of logical “1” on IO pin DQ0, indicating a failed parallel bit test.
Unfortunately, all pairwise bit comparisons in the method illustrated in FIG. 1 take place between bits in the same memory block. However, defective memory cells in the same memory block may be correlated, and therefore even if the parallel bit test indicates that both memory cells in a pair store the same data, it is likely that both memory cells in a pair are defective and that the parallel bit test will fail to identify those defective memory cells. In addition, the bit comparisons are fixed so that only a limited number of test patterns can be used to test whether the memory cells are functioning correctly. For example, the only test patterns that can be used to test memory cells in memory block 10 are “0000”, “1010”, “0101”, and “1111”. This limited number of test patterns can also prevent defective memory cells from being discovered. As a result, it is difficult for the conventional method parallel bit test method to detect all of the defective memory cells in a semiconductor memory device.